Nanosheet process flows usually begin with an silicon-on-insulator (SOI) wafer. See, for example, U.S. Pat. No. 8,422,273 issued to Chang et al., entitled “Nanowire Mesh FET with Multiple Threshold Voltages” (hereinafter “U.S. Pat. No. 8,422,273”). With an SOI wafer, isolation between adjacent devices is provided by way of the buried insulator (often an oxide referred to as a buried oxide or BOX). For instance, as described in U.S. Pat. No. 8,422,273, the SOI layer present on the BOX serves as the first layer in a nanosheet stack. SOI technology however requires additional processing steps such as wafer bonding or oxygen implantation to create the buried insulator beneath the SOI layer.
Thus, for ease and efficiency of manufacture, improved techniques for nanosheet isolation would be desirable.